1. Field of the Invention
This invention relates generally to data processing systems and, more particularly, to data processing systems capable of performing vector operations in a virtual memory environment.
2. Description of the Related Art
In order to increase the performance of certain types of repetitious operations, the technique of vector data processing operations has been developed. For example, a vector add operation can be used to add the corresponding elements of two data arrays together and store the resultant sums in a third array. This procedure can be contrasted with scalar instructions implementing the same computation which would require repeated execution of a loop routine. Vector processing has the advantage of specifying, in a single operation, the processing of large amounts of data without the need to issue multiple instructions or perform loop iteration control. In addition, since the same operation is being applied to each set of operands, pipelining techniques can be efficiently employed to increase performance. In general, two models of vector processing have emerged, the register based model and the memory based model.
In the resister based model, sets of operands are transferred (loaded) from main memory and stored in special registers referred to as vector registers. Each vector register can store a multiplicity of operands, each operand having a predetermined length. When one or more vector registers have the required operands stored therein, then all the operands stored in the vector registers are processed by a common arithmetic operation and the operands resulting from the processing operation are stored in a target vector register. Because the same operation is performed on all the operands of the vector registers, only one instruction need be issued to the processing execution unit to manipulate a multiplicity of operands. After all the requisite operations are performed on the set of operands, the operands are returned to (or stored in) the main memory unit.
In the memory based model, the operands are transferred directly from the main memory unit to the execution unit and the resulting operands are returned directly to the main memory unit. The memory based model theoretically provides higher performance because the information does not have to be stored into vector registers before starting an operation and then returned to memory when the operation is complete. However, when a vector operation is started, a certain amount of time is required before the first operand arrives from memory and therefore the memory based vector model is most efficient when the start up time can be amortized over a very long vector operation.
The vector register based model typically has very short start-up times and therefore has better performance on short vectors. Operands are loaded and stored in parallel with the actual vector operations and therefore the benefit of short start-up times is combined with maximum memory utilization to obtain nearly the same peak vector operation rates that are obtainable on long vector operations in the memory based model.
In modern data processing systems, the use of virtual memory has become so common as to be a requirement of a data processing system. In the virtual of the memory data processing system, the bulk of the logic signal groups required by the processor are stored in bulk storage units (also referred to as the backing store). When instruction and data elements are required by the data processing system, the data processing system anticipates that the requested instruction or data elements are stored in the main memory unit and, therefore, the data processing system attempts to transfer the required instruction or data element from the main memory unit to the portion of the data processing unit requiring the instruction or data element. When the data processing system determines that the requisite instruction or data element is not in the main memory unit, then a page fault is generated, the page being the unit of information stored in mass memory manipulated by the data processing system. The page fault causes data processing system apparatus to store information necessary to respond to the page fault and then transfers control to the operating system to respond to the page fault.
In response to the generation of a page fault, the data processing system will transfer control to an appropriate operating system module that will determine the location of the required instruction or data element, and transfer a "page" of instruction and/or data elements including the requested instruction or data element to the main memory unit. The operating system module will, in addition, create the tables required to relate the main memory address to the position of the requisite instruction or data element in the mass memory media.
In the scalar (nonvector) mode of operation, memory reference instructions are executed sequentially and can access only a single piece of data. When a datum is referenced that is not in main memory, necessary information is stored and a page fault exception is generated. The operating system gains control, reads the necessary page into memory, and then resumes program execution simply by backing up the program counter and continuing the execution of the instruction sequence.
In contrast, a single vector load or store operation can read or write up to the number of data element operands that can be stored in a vector register. While the vector load/store operation is being performed, it is advantageous to continue to issue additional vector and/or scalar instructions. Therefore, unlike the case of a scalar load/store operation, several additional instructions may have been issued after the vector instruction, but before the missing page(s) is (are) encountered. When the required data element is not in the main memory unit, several pieces of information must be preserved in order to restart or complete the execution of the instruction after the missing page has been transferred into the main memory unit.
The performance of the data processing system in performing vector operations can be limited by the memory speed, by how many vector load and store operations can be executed simultaneously, and by how many function or execution units can be operated in parallel performing the vector operations. Clearly, to the extent that multiple overlapping scalar and vector operations can be performed, the efficiency of the data processing system can be improved.
However, the execution of overlapping scalar and vector instructions in the virtual memory environment increases the difficulty of recovering from a page fault (i.e., when required data is not available in the main memory unit) resulting from the vector instruction. In fact, more than one vector operation can potentially have a page fault identified therewith during the completion of the currently executing instructions further complicating restart of the vector processing operations. With scalar load/store operations that reference a single piece of data, a memory management problem is immediately detected and therefore additional instructions are not issued. In order to optimize performance, instructions continue to be issued before a memory management problem can be detected for a vector instruction. The intervening instructions may have altered the state of information that was an operand of the original vector instruction and therefore, retrieval of the missing page, backing-up the program counter and re-executing the instruction may not provide an adequate response to the page fault. A need has therefore been felt for a technique that can permit relatively convenient recovery from page faults or other vector exceptions in a data processing system executing a plurality of overlapping vector operations using a vector register base model.